1. Field of the Invention
The invention relates to bus arbitration protocols, and particularly to a protocol on a bus where cycles can be aborted and retried.
2. Description of the Related Art
The performance demands on personal computers are ever increasing. It has been determined that a major bottleneck in improving performance is the capability to perform input/output (I/O) operations. Processor speeds continue to increase at a great rate and memory speeds and architectures can partially keep pace. However, the speed of I/O operations, such as disk and local area network (LAN) operations, has not kept pace. The increasing complexity of video graphics used in personal computers is also demanding greater performance then can be conventionally provided.
Some of the problems were in the bus architecture used in IBM PC-compatible computers. The EISA architecture provided some improvement over the ISA architecture of the IBM PC/AT, but more performance was still required. To this end Intel Corporation, primarily, developed the Peripheral Component Interconnect (PCI) bus. The PCI bus is a mezzanine bus between the host or local bus in the computer, to which the processor and memory are connected, and the I/O bus, such as ISA or EISA. For more details on the PCI bus, reference to the PCI Standard Version 2.0, from the PCI Special Interest Group in care of Intel Corp., which is hereby incorporated by reference, is advised. The bus was designed to have a high throughput and to take advantage of the increasing number of local processors that support I/O functions. For example, most disk controllers, particularly SCSI controllers, and network interface cards (NICs) include a local processor to relieve demands on the host processor. Similarly, video graphics boards often include intelligent graphics accelerators to allow higher level function transfer. Typically these devices have the capability of operating as bus masters, to allow them to transfer data at the highest possible rates.
Because of the number of potential devices trying to be bus masters, an arbitration scheme is required. A common arbitration scheme is least-recently-used (LRU). In certain cases, such as described in Application Serial No. 07/955,499, entitled Prioritization of Microprocessors in Multiprocessor Computer Systems, filed on Oct. 2, 1992, which is hereby incorporated by reference, the LRU scheme is modified so that the LRU of just the various requestors is utilized. This avoids potential deadlock conditions.
According to the PCI standard, responding devices may abort a cycle, causing the requesting device to retry the operation at a later time. This is desirable where numerous bus masters are present, as the bus is not held essentially inactive while waiting to gain control of another bus. By aborting the operation, other bus masters can gain access to the bus and perform operations, thus reducing the degradation of overall system performance. But if the responding device becomes available to complete the operation, it would be advantageous to allow the aborted requestor to gain quick control of this bus. Such a condition was present in the arbitration described in the above-referenced patent application, which system did not use the PCI standard. If a host bus master attempted to perform a locked cycle to the EISA bus and the EISA bus was busy, a reservation bit identifying the aborted requestor was set so that when the bus master next tried to access the bus on its retry operation and the EISA bus was available, the normal arbitration prioritization was overridden and the bus master having the reservation bit became the next bus master. This reservation technique was necessary as the aborted bus master become the most recently used and thus went to the bottom of the priority schedule.
To prevent the bus master from repeatedly requesting the bus and then being aborted, a signal was present on the bus so that the bus master did not request the bus until it could perform the locked cycle. However, the PCI standard does not make provision for this additional signal, so the techniques could not be readily utilized. Should a similar reservation technique be utilized with a PCI bus, thrashing of the bus by the high priority bus master could result, thus actually reducing system performance. A solution to resolve the problems of both a retried bus master becoming the lowest priority and of thrashing the bus when retrying is desirable in a PCI system.
Further, write posting buffers are commonly utilized to allow a write operation to be captured and performed as time permits, but the bus master is released to commence the next operation. In certain PCI designs the memory system utilizes such posting buffers. If the memory system is busy or the posting buffers must be flushed to main memory, the bus master's cycle may be aborted. If the main memory system were to have a low priority, the flush operation might be delayed until the main memory becomes the natural winner of a bus arbitration. However, this wait would also have delayed operation of the retrying bus master, as it must wait for the main memory to obtain priority. This increased delay reduces system performance, so a solution to this problem is desirable, allowing an increase in performance.
Thus, while the PCI bus is an improvement over prior buses, certain reduced performance conditions are present and their resolution is advantageous.